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Freescale Cadence model-based physical and electrical

    Cadence Design Systems (CDNS) today announced that Freescale Semiconductor through the use of Cadence's "design once successful" prevention, analysis, implementation and signoff solutions for successful implementation of a network of 45-nanometer chip design flow,booster cables the solution can help speed up the amount of production time and increase predictability.
    This process combines industry-leading, model-based design for manufacturing (DFM) prevention, analysis and signoff,battery clip including the Cadence Litho Physical Analyzer (LPA), Cadence Chemical-Mechanical Polishing Predictor (CCP), Cadence Litho Electrical Analyzer (LEA ), Cadence QRC Extraction Cadence Encounter digital implementation and adoption of the system (EDI System) implementation of model-based route optimization technology. DFM traditional solutions, tow rope this seamless approach can significantly speed up the turnaround time (TAT), we will use it in Chartered Semiconductor (Chartered Semiconductor Manufacturing) cast film design.

    "For the use of advanced process nodes, high-capacity design, we believe it is to achieve the accuracy of the chip and in lithography and chemical mechanical polishing (CMP) and other key steps to achieve an important driving factor in yield and differential factors," Freescale Semiconductor DFM technology manager Kyle Patterson said,ratchet tie dowm "through the integration of Cadence's advanced DFM technology, both in the physical implementation or an electrical implementation, we are able to accurately predict the manufacturability of the problem and prevent its emergence, compared with traditional DFM methods, This method requires less time. Basically, it allows us to accelerate time to market and production time. "

    Freescale, etc. with the cooperation of leading semiconductor companies, Cadence developed the industry's most comprehensive DFM a prevention, analysis and design methodology sign in support of optimization in the design side, to reduce risks for manufacturing. Cadence solutions leverage multi-core distributed processing approach to seamlessly meet the increasingly stringent requirements of the design cycle, and 45 nm, 32 nm node, expand the database capacity requirements, validated, this method can provide near linear scalability. In addition, LEA is the industry's first used in the production of electrical DFM (eDFM) solution, which is widely used for leading semiconductor companies from 90 nm to 40 nm process, and is used to promote the 32-nm and 28 nm variation awareness ( Variability-Aware) library development.

    "Our shared vision is to be accurate at the design stage to learn that model and its effects can be created to solve," Chartered DFM services senior manager Kuang-Kuo "KK" Lin, MD, "By working with Cadence to develop for Analysis and digital implementation of silicon-based DFM model accuracy, we have developed a set of Freescale significant advantage of DFM process, to speed up the completion of the design cycle "

    "45 nanometer and 32 nanometer process design, manufacturing complexity and tight budget request for customers, foundries and EDA partners early in the tripartite cooperation between the Freescale design in the success of this complex proved that if three closely how good results can be achieved when, "Cadence Design Systems Digital Implementation Solutions Director David Desharnais said," We are very pleased to see our products tested by the Encounter chip solutions that enable Freescale to establish and confirm from the cell library start, end products based on considerations of DFM awareness of the design process, we look forward to continue to deepen cooperation in the future to achieve a more advanced design methods and best practices. "

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