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DDR test whether the technology is to keep up with the times?

    DDR is double data rate SDRAM memory, and now most computer systems, servers, mainstream memory technology products, and continues to penetrate the embedded systems applications.

    As everyone knows, with the iPhone, big smart phone adoption, DDR memory has become one of the smart phone the direction of change, for example, to the end of Pantech's new Android smart phone equipped with a 512MB Vega X to the DDR2 memory.

   DDR technology development, parallel bus to serial technology, the speed, the clock speed of 1GHz. Currently, DDR3 is now available 1.6Gb / s data rates, while the DDR3-1866 and higher rate version is under development and will soon appear on the market. The current mainstream DDR2 also has a variety of speed, a variety of capacities and a variety of specifications, from the DDR-266 of 266MT / S, 133MHz, 2.5V voltage, has been developed to the current DDR2-1066 to 1066MT / S, 533MHz, 1.8V Voltage . In addition, low-power DDR (LP-DDR,ratchet tie dowm for portable computers) and also the DDR GDDR memory versions of the development and changes. Currently there are a variety of mainstream DDR speed, a variety of capacities and a variety of specifications, from the DDR-266 of 266MT / S, 133MHz, 2.5V voltage, has been developed to the current DDR3-1600, 1.5V voltage. In addition, low-power DDR (LP-DDR, for portable computers) is also one of the development trend of DDR.

   Technology upgrading and expansion of application fields, all the DDR memory validation and test more challenging. High data rate and clock speed makes the timing margin is more tension, leading to crosstalk, impedance matching, and jitter increase, which requires high-speed test and measurement technology and higher performance test and measurement tools to get better signal capture, measurement accuracy and so on.

   DDR test points and difficulties.

   View of the DDR's stub (short) topology and timing of tension tolerance, validation and testing requirements in a variety of test targets, including: electrical power and signal power quality, noise, glitches and ground bounce / to jump; clock signal quality, rise time and fall time / slew rate; command, address and data valid window (setup / hold time); DQS / DQ / clock skew.

   DDR data rates makes the storage system and improve signal integrity issues become increasingly prominent. Therefore, the signal must be the physical layer and system-level associate timing to avoid timing conflicts, protocol deviation, clock jitter, and errors caused by the bus, to ensure the accuracy of the storage system work. Need to associate the timing include: memory initialization sequence; SDRAM mode register operation (MSR); read / write data valid window; dormant timing; normal working state timing.

   As for the DDR test difficulty, the Tektronix Technical Support Engineer I-lan IIC-China recently a symposium pointed out: "First, DDR data signals DQ and DQS are bidirectional, so the read signal and write signal will appear in the data line, the data is more difficult to separate the data which data is read write data; second, is to explore the problem, DDR2 or 3 using a BGA package, pin hidden in the bottom of the chip, so the choice is very important probe . In addition, as a very high rate of DDR2 and DDR3, so for the bandwidth and signal fidelity requirements of detection is particularly high, and many times we rely on the oscilloscope has failed to meet the test requirements, the need to join such as the logic analyzer and protocol, etc. timing of the joint test. "

   Yu Lan said, bandwidth / rise time, sampling rate, trigger mode, memory software oscilloscope probe is DDR an important consideration in test selection indicators, bandwidth / rise time is the most important, including connectivity, signal fidelity. But the need to combine logic analyzer and other equipment, the channel number and sampling rate is the most important consideration.

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